A data receiver circuit which receives data transmitted through a transmission channel recovers data and a clock from a received signal using a clock/data recovery circuit. In data transmission, a phase difference between data and a clock cannot be ignored when, for example, data rate is high and/or a transmission distance is long. Therefore, data and a reference clock (a clock obtained by dividing the frequency of a clock recovered from the data) are outputted to a circuit at the subsequent stage, and the data and the clock are recovered by the clock/data recovery circuit in the circuit at the subsequent stage.
However, in a conventional data receiver circuit, when an input signal is lost or an S/N ratio of the input signal is low, the data receiver circuit outputs data in which 0 or 1 continues. In this case, the clock/data recovery circuit at the subsequent stage can not lock the data. In addition, a clock outside of a prescribed range is outputted. That is to say, such abnormal data in which 0 or 1 continues is outputted from the data receiver circuit, the data receiver circuit at the subsequent stage does not operate normally.
As described above, when the input signal is lost or the clock/data recovery circuit goes into the loss-of-lock state, the conventional data receiver circuit outputs abnormal data in some cases.
As a related art, there has been proposed an optical receiver/amplifier circuit which is configured to generate a signal indicating stop of optical input based on a first stop detection signal indicating the stop of the optical input and a second stop detection signal which is detected in relation to any of the optical receiver/amplifier circuit, a clock recovery circuit, and an optical detector. (For example, Japanese Laid-Open Patent Publication No. 2000-332720)
In addition, as another related art, there has been proposed an optical digital transmission apparatus having a configuration in which a PN pattern generation circuit to generate a PN pattern which is a random pattern having a mark ratio of 1/2 is provided on a receiver side, and the PN pattern is inserted when a low-order group signal is not inputted, whereby the PN pattern is detected by the receiver side. (For example, Japanese Laid-Open Patent Publication No. 2002-261718)